Nanocore MAXC32KIT1 and input capture of switch

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Nanocore MAXC32KIT1 and input capture of switch

Postby tdub » Mon Mar 05, 2007 5:01 pm

Hi, I was hoping someone could help me figure out a problem I'm having with my code. I want to use the SW3 on the Nanocore Max32 board as a stop switch on a robot I made. Basically I want to press the button which will cause the input capture iterrupt to jump to a subroutine that resets the motor controller. I can't seem to get the switch to trigger the interrupt routine. I have hooked up pin 12 (AN5) to pin 25 (PT0) because I understand input capture interrupts are only on PORTT. I have tested the switch by polling and it works fine, however, the interrupts are still not working. Any help you can offer would be great. Also, my code needs to be in assmebly language. Here is my code:

; A switch interrupt test program
;

REGBASE equ $0
RAMBASE equ $3800
INITRM equ $0010 ; RAM Position
INITRG EQU $0011 ; Register position

;SCI Registers

SCIBDH equ $00C8
SCIBDL equ $00C9
SCICR1 equ $00CA
SCICR2 equ $00CB
SCISR1 equ $00CC
SCISR2 equ $00CD
SCIDRH equ $00CE
SCIDRL equ $00CF


;PORTT registers
PORTT equ $0240
DDRT equ $0242

;Timer registers

TCTL3 equ $004A ; Timer Control Register 3
TCTL4 equ $004B ; Timer Control Register 4
TIOS equ $0040 ; Timer Input Capture/Output Compare Select
TIE equ $004C ; Timer Interrupt Enable Register
TFLG1 equ $004E ; Main Timer Interrupt Flag 1
TSCR1 equ $0046 ; Timer System Control Register1
TSCR2 equ $004D ; Timer System Control Register 2
TC0H equ $0050 ; Timer Input Capture/Output Compare Register 0



;PLL Registers

SYNR equ $34
REFDV equ $35
CRGFLG equ $37
CLKSEL equ $39
PLLCTL equ $3A
COPCTL equ $3c


org $3800

myflag rmb 1

org $8000 ; start of program memory

BadInt ; handle UNexpected interrupts...
rti

startup_code

sei ; Disable interrupts
movb #$00,INITRG ; set registers to $0000
movb #$39,INITRM ; init RAM ($3800 - $3fff)
lds #$3fce ; init stack
cli

bclr CLKSEL, #$80 ; disengage PLL to system
bset PLLCTL, #$40 ; turn on PLL
movb #$2, SYNR ; set PLL multiplier
movb #$0, REFDV ; set PLL divider
nop
nop
brclr CRGFLG,#$08,>*+0 ; while (!(crg.crgflg.bit.lock==1))
bset CLKSEL, #$80 ; engage PLL to system

serial_setup:

;BUSCLK is running at 24MHz, so we'll base all speeds on that.

movb #$00,SCIBDH ; set the SCI baud rate to 9600 bits/sec
movb #$9C,SCIBDL ; 9600=24x10^6/(16*156), $9c=156
movb #$0c,SCICR2 ; Turn on the SCI transmitter and receiver

;------------------------------------------------------------------
; User Program - send out the ASCII codes for symbols from 0 to z ($30 through $7a)
;------------------------------------------------------------------

USER_START:
movb #$40, COPCTL ; COP off; RTI and COP stopped in BDM-mode
clr myflag

setup_portt:
movb #$fc, DDRT ; make pins 2-7 o/p and pins 0-1 i/p ports on PORTT
movb #$00, PORTT ; initialize PORTT

setup_tim:
movb #$00,TCTL3
movb #$02,TCTL4 ; setup edge detection for falling edge
movb #$01,TIE ; using PT0
movb #$01,TFLG1 ; using PT0

cli



switch:
movb #$30,myflag

tx_data:
brclr SCISR1,#$80,tx_data


ldaa myflag ; will transmit an ASCII 0 when no int and a 2 when int
staa SCIDRL
jmp switch



test_int:
movb #$32,myflag

test_int_exit:
movb #$01,TFLG1
rti



; ------------------ VECTOR TABLE --------------------
org $FF8A
fdb BadInt ;$FF8A: VREG LVI
fdb BadInt ;$FF8C: PWM emergency shutdown
fdb BadInt ;$FF8E: PortP
fdb BadInt ;$FF90: Reserved
fdb BadInt ;$FF92: Reserved
fdb BadInt ;$FF94: Reserved
fdb BadInt ;$FF96: Reserved
fdb BadInt ;$FF98: Reserved
fdb BadInt ;$FF9A: Reserved
fdb BadInt ;$FF9C: Reserved
fdb BadInt ;$FF9E: Reserved
fdb BadInt ;$FFA0: Reserved
fdb BadInt ;$FFA2: Reserved
fdb BadInt ;$FFA4: Reserved
fdb BadInt ;$FFA6: Reserved
fdb BadInt ;$FFA8: Reserved
fdb BadInt ;$FFAA: Reserved
fdb BadInt ;$FFAC: Reserved
fdb BadInt ;$FFAE: Reserved
fdb BadInt ;$FFB0: CAN transmit
fdb BadInt ;$FFB2: CAN receive
fdb BadInt ;$FFB4: CAN errors
fdb BadInt ;$FFB6: CAN wake-up
fdb BadInt ;$FFB8: FLASH
fdb BadInt ;$FFBA: Reserved
fdb BadInt ;$FFBC: Reserved
fdb BadInt ;$FFBE: Reserved
fdb BadInt ;$FFC0: Reserved
fdb BadInt ;$FFC2: Reserved
fdb BadInt ;$FFC4: CRG self-clock-mode
fdb BadInt ;$FFC6: CRG PLL Lock
fdb BadInt ;$FFC8: Reserved
fdb BadInt ;$FFCA: Reserved
fdb BadInt ;$FFCC: Reserved
fdb BadInt ;$FFCE: PORTJ
fdb BadInt ;$FFD0: Reserved
fdb BadInt ;$FFD2: ATD
fdb BadInt ;$FFD4: Reserved
fdb BadInt ;$FFD6: SCI Serial System
fdb BadInt ;$FFD8: SPI Serial Transfer Complete
fdb BadInt ;$FFDA: Pulse Accumulator Input Edge
fdb BadInt ;$FFDC: Pulse Accumulator Overflow
fdb BadInt ;$FFDE: Timer Overflow
fdb BadInt ;$FFE0: Standard Timer Channel 7
fdb BadInt ;$FFE2: Standard Timer Channel 6
fdb BadInt ;$FFE4: Standard Timer Channel 5
fdb BadInt ;$FFE6: Standard Timer Channel 4
fdb BadInt ;$FFE8: Standard Timer Channel 3
fdb BadInt ;$FFEA: Standard Timer Channel 2
fdb BadInt ;$FFEC: Standard Timer Channel 1
fdb test_int ;$FFEE: Standard Timer Channel 0
fdb BadInt ;$FFF0: Real Time Interrupt (RTI)
fdb BadInt ;$FFF2: IRQ (External Pin or Parallel I/O) (IRQ)
fdb BadInt ;$FFF4: XIRQ (Pseudo Non-Maskable Interrupt) (XIRQ)
fdb BadInt ;$FFF6: Software Interrupt (SWI)
fdb BadInt ;$FFF8: Illegal Opcode Trap ()
fdb startup_code ;$FFFA: COP Failure (Reset) ()
fdb BadInt ;$FFFC: Clock Monitor Fail (Reset) ()
fdb startup_code ;$FFFE: /RESET
tdub
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Postby erarama » Mon Mar 05, 2007 7:39 pm

See appnote
http://support.technologicalarts.ca/doc ... noCore.pdf

YOu need to enable TEN in TSCR1 register
erarama
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Location: Canada

Postby tdub » Mon Mar 05, 2007 8:56 pm

That fixed it. Thanks you. My project is complete now.
tdub
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